Among liquid crystal display devices of various display schemes, there is an active-matrix liquid crystal display device using a TFT (Thin Film Transistor) for a switching element, as a liquid crystal display device capable of providing display with high resolution.
As illustrated in FIG. 13, an active-matrix liquid crystal display device 110 is broadly divided into a liquid crystal display section 110a and a liquid crystal drive circuit 110b serving as a liquid crystal drive unit which drives the liquid crystal display section 110a. 
The liquid crystal display section 110a has a TFT liquid crystal panel 101. The liquid crystal drive circuit 110b includes a source driver 103 and a gate driver 104 each of which is realized by IC (Integrated Circuit; semiconductor integrated circuit), a controller 105, and a liquid crystal drive power source 106.
In the liquid crystal display device 110 of the above arrangement, externally supplied display data is supplied as display data D, which is a digital signal, through the controller 105 to the source driver 103. The source driver 103 latches the supplied display data D by time division into first to n-th source drivers. Thereafter, the source driver 103 performs D/A (digital/analogue) conversion on the time-divided display data D into an analogue voltage for grayscale display (hereinafter, referred to as “grayscale display voltage”) in synchronism with a horizontal synchronizing signal fed from the controller 105. Then, the source driver 103 outputs the grayscale display voltage via source signal lines (not shown) to the respective liquid crystal display elements in the liquid crystal panel 101.
Meanwhile, as illustrated in FIG. 14, the liquid crystal panel 101 includes a pixel electrode 111, a pixel capacity 112, a TFT (Thin film Transistor) 113 which performs on/off controls for voltage application to the pixel electrode, a source signal line 114, a gate signal line 115, and a counter electrode 102. Here, the pixel electrode 111, the pixel capacity 112, and the TFT 113 make up a liquid crystal display element A that represents one pixel.
To the source signal lines 114, the grayscale display voltages responsive to luminance levels of target pixels are fed from the source driver 103 illustrated in FIG. 13. To the gate signal lines 115, scanning signals sequentially turning on the TFTs 113 aligned in rows are fed from the gate driver 104. Then, via the ON-state TFT 113, the grayscale display voltage of the source signal line 114 is applied to the pixel electrode 111, which is connected to a drain of the corresponding TFT 113, and the grayscale display voltage is accumulated in the pixel capacity 112, which is provided between the pixel electrode 111 and the counter electrode 102. In this manner, light transmittance of the liquid crystal varies with the grayscale display voltage for display of a pixel.
Next, an n-th source driver that is one of the constituent elements making up the source driver 103 will be described with reference to FIG. 15.
As illustrated in FIG. 15, in an n-th source driver 130, the incoming display data D, digital signal, has display data (DR, DG, DB) of R (red), G (green), and B (blue). The display data D is temporarily latched by an input latch circuit 131, and then stored in a sampling memory circuit 133 by time division, in accordance with operation of a shift register circuit 132 which shifts with a start pulse SP and a clock CK from the controller 105. Thereafter, the display data D is transferred to a hold memory circuit 134 at one time in accordance with a horizontal synchronizing signal (not shown) from the controller 105. “S” in FIG. 15 is cascade output.
A grayscale display reference voltage generator circuit 139 generates reference voltages of different levels in accordance with a voltage VR fed from an external reference voltage generator circuit (equivalent to the liquid crystal drive power source 106 illustrated in FIG. 13). Data of the hold memory circuit 134 is transmitted through a level shifter circuit 135 to a D/A converter circuit 136 to convert them into analogue voltages in accordance with reference voltages of difference levels. Then, an output circuit 137 causes liquid crystal drive voltage output terminals 138 (terminals R1, G1, B1-Rn, Gn, Bn represented in FIG. 15) to output the converted analogue voltages as the grayscale display voltages to the source signal lines 114 of the liquid crystal display elements A. That is, the number of the reference voltage levels indicates the number of grayscale levels.
The grayscale display reference voltage generator circuit 139 which generates the foregoing reference voltages to generate intermediate voltages generates, for example, 64 levels of reference voltages, as illustrated in FIG. 16.
The grayscale display reference voltage generator circuit 139 is composed of: nine halftone voltage input terminals represented by V0, V8, V16, V24, V32, V40, V48, V56, and V64; resistor elements R0 through R7 having resistance ratio for γ correction; a total of 64 resistors including groups of 8 resistors connected across each of the resistor elements R0 through R7. In this manner, the source driver 103 includes resistance ratio called γ correction so that liquid crystal drive output voltages for converting into the grayscale display voltages have broken line characteristic. Consequently, optical characteristics of liquid crystal material are corrected by using the resistance ratio, so that natural grayscale displays can be provided according to the optical characteristics of the liquid crystal material. FIG. 17 illustrates an example of characteristics of γ-corrected liquid crystal drive output voltages in the conventional grayscale display reference voltage generator circuit 139.
Next, the gate driver 104, as illustrated in FIG. 18, includes a control logic 161, a bidirectional shift register 162, a level shifter 163, an output circuit 164, and others. The gate driver 104 includes terminals for receiving a start pulse signal SP, a clock signal CK, a power-supply voltage VCC, a ground voltage GND, and voltage VDD, and multiple output terminals OS1 through OSn.
The control logic 161 generates a signal required for operation of the bidirectional shift register 162 and then supplies the generated signal to the bidirectional shift register 162. When receiving the clock signal CK and the start pulse signal SP, the bidirectional shift register 162 carries out a shift operation to sequentially bring the start pulse signal SP into sync with the clock signal CK. The bidirectional shift register 162 generates a select pulse and then outputs it to the level shifter 163. The select pulse is the one for selecting from the liquid crystal panel 101 a pixel electrode to be driven by voltage applied from the source driver 103 to the source signal line 114. The level shifter 163 converts a voltage of the select pulse into a voltage at a level required for on/off (selected/non-selected) of the TFT element 113 in the liquid crystal panel 101, and outputs it to an output circuit 164.
In accordance with the signal fed from the level shifter 163, the output circuit 164 applies a voltage at a level required for on/off of the TFT element 113, via the respective output terminals OS1 through OSn, to the gate signal lines 115. That is, as illustrated in FIG. 19, for example, when the output circuit 164 receives an input signal of voltage VCC, the output circuit 164 sequentially supplies an output signal of voltage VDD to the output terminals OS1 through OSn. On the other hand, when the output circuit 164 receives no input signal (voltage GND), the output circuit 164 supplies an output signal of voltage. VSS to the output terminals OS1 through OSn.
Incidentally, in such a conventional display element drive unit, all display control input signals are supplied through the controller 105 illustrated in FIG. 13. Therefore, in a state of the display element drive unit right after a panel running power is turned on but before operation of the controller is initiated, since neither display data signal nor input control signal are supplied respectively to the source driver 103 and the gate driver 104 both of which are illustrated in FIG. 13, voltages of the driver output terminals supplied to the liquid crystal panel 101 are in unstable levels.
For this reason, due to voltage levels of gate elements on the panel at power-on, unstable voltages are added to the source voltages. This might cause instantaneous unexpected displays on part of the scanning lines or over the entire panel.
In order to avoid such a phenomenon, Japanese Laid-Open Patent Application No. 4244/2004 (Tokukai 2004-4244; published on Jan. 8, 2004), for example, adopts a technique of outputting another given voltage to a panel electrode or an external counter electrode CS by a switch of output switch means which is provided between grayscale selection means (D/A converter) and a liquid crystal panel electrode.
However, in the conventional display element drive unit, since a technique of Japanese Laid-Open Patent Application No. 4244/2004 has a necessity for reducing resistance of switch means (analogue switch or the like) to prevent a voltage drop of the grayscale display voltage, it has the problem of an extremely large circuit area for switch means (analogue CMOS or the like) which switches to an analogue voltage converted by the D/A converter.
More specifically, in the arrangement having the voltage level switch means realized by an analogue switch as illustrated in FIG. 20, in a display element drive unit, a D/A converter 201 generally converts the display data into analogue grayscale select voltage, and an output circuit 202 using an operational amplifier circuit, for example, causes the analogue grayscale select voltage to have low impedance so as to output analogue voltage as a liquid crystal pixel source voltage A.
At the point, in the case where the arrangement of Japanese Laid-Open Patent Application No. 4244/2004 is adopted, for example, provision of a switch 210 for supply of a pixel voltage to a counter electrode is considered as illustrated in FIG. 20 to apply a given voltage to a liquid crystal pixel or output it to an external counter electrode CS during a given period right after the power-on.
However, in the arrangement where the switch 210 is provided at the subsequent stage of the output circuit 202 in which the analogue grayscale select voltage resulting from analogue conversion is subjected to low-impedance processing, a resistance impedance is applied to the liquid crystal pixel source voltage A that is an analogue voltage having a low impedance, before reach to the corresponding pixel. Since this resistance impedance component affects, for example, analogue time constant, transient characteristic, or a pixel voltage switching speed such as a voltage drop caused due to a delay of a reach time with increase in slew rate, it is necessary to design an extremely low on-resistance of the analogue switch section 211 according to panel characteristics. Therefore, in the arrangement in which this switch is realized by an analogue circuit which needs to withstand a voltage to some extent, a transistor of large size has to be designed with a design of low on-resistance. This causes a relative increase in circuit scale.
in addition, in order that the switch 210 inversely outputs a common voltage to supply it to a common electrode, an analogue switch section 211 needs to be of a buffer having an ability to cause a common voltage to make a transient response, and needs to be of a low impedance. Therefore, it is necessary to decrease a circuit impedance according to a drive performance of the common electrode, which thus causes a relative increase in circuit scale.